Certain embodiments of the present invention relate to processing of buffered digital signals. More specifically, certain embodiments relate to a method and apparatus for resetting a gray code counter associated with a video, voice and/or data buffer.
A gray code is a binary code in which consecutive decimal numbers are represented by a binary expression that differ in the state of one (1), and only one (1) bit. Accordingly, a gray code counter is a counter in which each successive binary count differs by one bit.
FIG. 1 is an exemplary finite state machine (FSM) 100 that may be used to implement a gray code counter. Referring to FIG. 1, the finite state machine 100, for example, may be used to implement a 4-bit counter, which may range from zero (0) to fifteen (15). Initial state 102 may represent binary state 0000 and a final state 110 may represent binary state 1000. Each consecutive state between initial binary state 102 and final state 110 vary by only one (1) bit. For example in state 104, a consecutive state to the initial state 102, only the least significant bit, bit four (4) changes. Similarly, in state 106, a consecutive state to the state 104, only the bit next to the least significant bit, bit three (3), changes. Similar single bit changes occur until the final binary state 110 is reached. At this point, a reset or a rollover occurs to the initial state 102, in which the binary values of the gray code counter changes from 1000 to 0000.
In certain applications, it might be advantageous to switch a single bit in any clock instant. For example, in integrated circuits (ICs), which may be prone to noise or which require a low noise environment for optimal operation or performance, gray code counters may be preferable over binary counters, the latter of which switches more than one bit at any clock instant. In general, the greater the number of bits being switched, the greater the amount of noise generated since each bit transition generates noise. Similarly, the lesser the number of bits number being switched, the lesser the amount of generated noise since there are less transitions to generate noise.
In general, gray code counters may be sampled asynchronously at any time during a given clock period. In this regard, since only one bit changes during any given transition, a maximum sampling error for a gray code counter is one (1). With binary counters, however, errors may occur with asynchronous sampling since some flip-flops (FF) used to implement the binary counter may have transitioned prior to or subsequent to a sampling instant. In this case, if the sampling instant occurs at or near a rising edge or a falling edge of a clock, then some FFs may have transitioned before others, thereby causing the errors.
Gray code counters may be particularly useful in applications that include, but are not limited to, asynchronous video, voice and data communication. In this regard, a gray code counter may be utilized for accessing certain video, voice and/or data buffers. In such applications, particularly with video applications, impairments such as noise and/or transients may cause errors in the gray code counter. In particular, since asynchronous clock signals may be used to control the buffers, a reset of the gray code counter may cause a non-gray code transition, which may result in glitching. In this case, the buffer may enter an undesired state, thereby causing a buffer status error.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.